In order to improve the degree of integration of a semiconductor integrated circuit, a channel length of a MOS transistor would be shortened. If a channel length of a MOS transistor is shortened, a hot-carrier implantation phenomenon would become remarkable, and therefore, a threshold voltage of the MOS transistor would be fluctuated. For suppressing generation of hot carriers, electrical filed around a drain region is decreased. A LDD structure, which includes a region having a lower density of impurities as compared to a drain region, has been used.
According to a LDD structure, a drain has a double-region structure including a first region with a lower density of impurity and a second region with a higher density of impurity, so that a depletion layer of the drain is extended not only to the channel region but also to the first region having a lower density of impurity. As a result, electric field near the drain region is reduced and weakened.
Japanese patent publication No. 2003-100771A describes a high voltage MOS transistor having a gate-overlap LDD (Lightly Doped Drain) structure, in which a gate electrode and a low density diffusion layer are overlapped.
FIGS. 1-1 to 1-9 illustrate fabrications steps of a high voltage MOS transistor according to a conventional technology. First, as shown in FIG. 1-1, element isolation regions 12 are formed in a p-type silicon substrate 10 by a STI process. Next, as shown in FIG. 1-2, a resist pattern 14 is formed on the silicon substrate 10 by a well-known photo-lithographic process.
Next, as shown in FIG. 1-3, phosphorus is implanted as impurities in the silicon substrate 10 using the resist pattern 14 as a mask to form a pair of low-density impurity-implanted regions 16 of n-type. The low-density impurity-implanted regions 16 are formed by an ion implantation process at 1.0×1013 cm−2. Next, as shown in FIG. 1-4, the resist layer 14 is removed. Next, as shown in FIG. 1-5, a gate oxide layer 18 is formed on the silicon substrate 10 to have a thickness of 500 Å by a thermal oxidation process. After that, a poly-silicon layer 20 is formed on the gate oxide layer 18 to have a thickness of 3000 Å by a CVD process.
Next, as shown in FIG. 1-6, a resist pattern 22 is formed on the poly-silicon layer 20 by a well-know photolithographic process. After that, as shown in FIG. 1-7, the poly-silicon layer 20 and the gate oxide layer 18 are etched using the resist pattern 22 as an etching mask to form a gate electrode.
Next, an oxide layer is formed on the silicon substrate 10 to have a thickness of 5000 Å by a CVD process. After that, as shown in FIG. 1-8, the oxide layer is shaped to form a side wall 24 on a side surface of the gate electrode 20 and on a side surface of the gate oxide layer 18 by an etching back process.
Next, arsenic of 1.0×1013 cm−2 is implanted into the silicon substrate 10 by a photolithographic process and an ion implantation process to form high-density impurity-implanted regions 26, as shown in FIG. 1-9. The high-density impurity-implanted regions 26 function as source and drain electrodes. After that, a thermal treatment is carried out so that impurities in the low-density impurity-implanted regions 16 are diffused to form low-density n-type impurity-diffused regions and impurities in the high-density impurity-implanted regions 26 are diffused to form high-density n-type impurity-diffused regions. According to the above described steps, a high voltage MOS transistor having a gate-overlap structure, is fabricated.
However, according to the above-described conventional technology, it is difficult to align a gate electrode and low-density n-type impurity-diffused regions directly to each other. If the gate electrode and the low-density n-type impurity-diffused regions are not located properly, the gate-overlap length between them would be fluctuated. As a result, characteristics of a MOS transistor would be fluctuated as well. A substrate current of a MOS transistor changes in accordance with the gate-overlap length. The more the gate-overlap length is shortened, the more the substrate current of a MOS transistor would be increased. In more detail, when the overlap length between the gate electrode and the low-density n-type impurity-diffused regions becomes lower than 0.5 μm, the substrate current of a MOS transistor would be rapidly increased. And therefore, a hot-carrier resistance of the MOS transistor would be remarkably decreased.
Japanese Patent Publication H05-243262A describes a method for controlling an overlap area between the gate electrode and the low-density n-type impurity-diffused regions by a self-alignment manner. According to a method described in Japanese Patent Publication H05-243262A, an etching mask having an opening is formed on a first gate electrode layer, then a second gate electrode layer is formed over the etching mask. Subsequently, the second gate electrode layer that is located on a side surface of the opening is selectively removed to form side openings. After that, impurities are implanted from the side openings into a semiconductor substrate to form low-density regions. Next, a coating layer is formed in the opening, and the first and second gate electrode layers are etched using the coating layer as a mask. Subsequently, high-density impurity regions are formed.
According to Japanese Patent Publication H05-243262A, the second gate electrode layer is etched before performing an ion implantation to form the low density impurity regions. When etching the second gate electrode layer, the dimension and shape of the side opening are defined by the difference of etching speed between a flat surface region and a side surface region. Therefore, the dimension of the side opening varies due to the thickness of the second gate electrode layer.
When the thickness of the second gate electrode layer varies, the dimension of the side openings varies as well, and therefore, the area or length of overlapped regions of the gate electrode and the low-density impurity-diffused regions varies. In another case, overlapped lengths vary in a single MOS transistor. Namely, according to the conventional technology, it is difficult to control an overlapped area or length of a gate electrode and low density impurity diffused regions precisely.